In order to reduce power consumption in a data processing system operating in synchronization with a clock signal, there have been proposed methods of supplying a clock signal from a circuit block which performs a process first to a circuit block which performs the process next. For example, each of circuit blocks operates upon receiving a clock signal when a clock enable signal is at a valid level. Related arts are discussed in Japanese Laid-open Patent Publication Nos. 2009-75973 and 2007-207121.
A clock enable signal is generated in accordance with an operation period of the circuit block, based on a program executed by a processor such as a CPU. Therefore, it is difficult to switch the clock enable signal very frequently and dynamically change the frequency of the clock signal according to the operation state of each of the circuit blocks. As a result, a fine power control may not be performed to reduce power consumption.